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[assembly language] serial-communication-source-code

Description: 这是一个有关于串口通信的原码，主要是用verilog语言来实现，采用的是模块联合方法。-This is a serial communication source code, verilog language, using the module combination method.
Platform: | Size: 21504 | Author: 孙良慧 | Hits:

[Other] 8-serial-parallel-conversion

Description: 用verilog硬件描述语言实现的8位串并转换-8 serial-parallel conversion
Platform: | Size: 29696 | Author: 丁凤 | Hits:

[VHDL-FPGA-Verilog] Verilog-Serial-communication

Description: Verilog在DE2实现串口通信，通过上位机给DE2发送数据，并反馈给上位机-Verilog serial communication in the DE2 DE2 send data through the host computer, and feedback to the host computer
Platform: | Size: 34816 | Author: Mr.wang | Hits:

[MiddleWare] Serial-parallel-multiplier-verilog-design

Description: Serial parallel multiplier verilog design source code
Platform: | Size: 27648 | Author: dorababugfree | Hits:

[VHDL-FPGA-Verilog] serial

Description: Verilog HDL编写的串口通信程序。-The Verilog HDL written serial communication program.
Platform: | Size: 348160 | Author: 陈 | Hits:

[VHDL-FPGA-Verilog] verilog--serial-port-communication

Description: 自己看了很多材料以后，精心整理的串口通信实验原理和指导，在网上找了很多代码，大部分因为没有很好的注释，看起来很头疼，于是自己写了一份，附带详细的注释，在modelsim仿真器上已经得到验证，现在传上来，仅供参考。-verilog codes for serial port communication
Platform: | Size: 140288 | Author: chenkun | Hits:

[VHDL-FPGA-Verilog] mmuart_latest.tar

Description: uuart 串口的verilog 源码实现，欢迎下载使用. uart 串口 verilog-uuart serial verilog source implementation, welcome to download
Platform: | Size: 3072 | Author: dodoo123 | Hits:

[Software Engineering] verilog-uart

Description: UART（Universal Asynchronous Receiver Transmitter，通用异步收发器）是广泛使用的异步串行数据通信协议。下面首先介绍UART硬件接口及电平转换电路，分析UART的传输时序并利用Verilog HDL语言进行建模与仿真，最后通过开发板与PC相连进行RS-232通信来测试UART收发器的正确性。-UART (Universal Asynchronous Receiver Transmitter, Universal Asynchronous Receiver Transmitter) is a widely used asynchronous serial data communication protocol. Below first introduced UART hardware interface and level conversion circuit, the UART transmit timing analysis and use of Verilog HDL language modeling and simulation, and finally the development board connected to the PC via RS-232 communications conducted to test the correctness of UART transceiver.
Platform: | Size: 117760 | Author: 李科 | Hits:

[VHDL-FPGA-Verilog] rs232

Description: rs232串口通信实验4位的串口，verilog源代码。-rs232 serial communication experiment 4 serial, verilog source code
Platform: | Size: 190464 | Author: 廖飞 | Hits:

[VHDL-FPGA-Verilog] serial-pc-verilog

Description: 串口 和 pc 端通信的verilog程序 ！适合初学者 ！ 代码简单 ，结构清晰！-Serial and pc client communication verilog program! Suitable for beginners! The code is simple, clear structure!
Platform: | Size: 77824 | Author: Narainel | Hits:

[VHDL-FPGA-Verilog] verilog-procedures

Description: fpga的基于verilog的串行数据转并行数据的相关资料，相关内容uart协议，串并转换程序-verilog fpga-based serial data to parallel data, relevant information, relevant content uart protocol string and conversion program
Platform: | Size: 1412096 | Author: | Hits:

[VHDL-FPGA-Verilog] serial-port-communication

Description: 实现串口通信的verilog代码，简述基本串口通信功能的实现-serial port communication verilog code
Platform: | Size: 2048 | Author: 徐以为 | Hits:

[VHDL-FPGA-Verilog] Verilog-Accumulator

Description: the folder contains two files written by Verilog HDL. the first one is an implementation of an accumulator that takes serial data as an input, and its output will be an accumulated sum of each consecutive four input samples. the second file is a test bench for the first file to test its operation
Platform: | Size: 1024 | Author: sawsan | Hits:

[VHDL-FPGA-Verilog] Verilog-interface

Description: 基于fpga的verilog语言 实现的串口接收发送数据编程-fpga serial
Platform: | Size: 1024 | Author: 时迁 | Hits:

[VHDL-FPGA-Verilog] verilog--uart--fpga

Description: 基于verilog的串口通信实验指导和源程序-Verilog based serial communication experiment guide and source code
Platform: | Size: 3122176 | Author: 宋江 | Hits:

[VHDL-FPGA-Verilog] UART-Verilog-source

Description: Verilog编写UART串口例程，实现FPGA与上位机串口通信，利用ASCII码进行大小写转换，在Xilinx Virtex-5开发板测试通过-UART serial routines written in Verilog, FPGA serial communication with the host computer using the ASCII code case conversion, in the Xilinx Virtex-5 development board test
Platform: | Size: 3072 | Author: charley | Hits:

[VHDL-FPGA-Verilog] Verilog-RS232

Description: 本程序是在FPGA里面模拟RS232串口，并在已调试成功。-This procedure is simulated in FPGA RS232 serial port, and in the debugging success
Platform: | Size: 3072 | Author: yz | Hits:

[Other] FPGA-rs232(verilog)-2

Description: FPGA rs232串口收发程序，3个程序任意选择，全部可用-FPGA rs232 serial transceiver procedures, three procedures arbitrarily selected, all available
Platform: | Size: 100352 | Author: xy | Hits:

[VHDL-FPGA-Verilog] serial-ports2

Description: verilog语言 12位串行数据传输转换为并行传输-12bit parallel to serial decoder and aynthesis result
Platform: | Size: 628736 | Author: eric | Hits:

[VHDL-FPGA-Verilog] serial-cordic-verilog

Description: implementation of cordic algorithm for many aplication like cos, sinus, polar to rectangular conversion and rectangular to polar conversion. It s written in verilog language and testbench is included
Platform: | Size: 3072 | Author: appolo | Hits:
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